1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a multilayer wiring structure where a low dielectric-constant film is used as an insulating layer.
2. Description of Related Art
In recent years, as LSIs (MOSLSIs) including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) have proceeded toward fine patterning and multi-layering of lines as well as fine patterning of elements such as a MOSFET, there is a growing demand to increase an access speed. To meet such demand, a low-resistance material is used for a wiring layer, and a dielectric-constant film (Low-k film) having a low dielectric constant is used as an insulating layer between wiring layers.
FIGS. 10 and 11 show an example of a conventional semiconductor integrated circuit device where a low dielectric-constant film is used for an insulating layer. FIGS. 10 and 11 schematically show the structures of an input/output pad and a protective element of the conventional semiconductor integrated circuit device. FIG. 10 is a plan view of a conventional semiconductor integrated circuit device 900. FIG. 11 is a sectional view of FIG. 10.
As shown in FIG. 11, in the conventional semiconductor integrated circuit device 900, a protective element 951 and an input/output pad 952 are formed on or above a semiconductor substrate 910. A protective element 951 has a diffusion region 911, a diffusion region 912, and a gate electrode 913. The protective element 951 and the input/output pad 952 are electrically connected together.
N wiring layers and N insulating layers are laminated on a main surface of the semiconductor substrate 910. As shown in FIG. 11, metal lines 901 to 905 are formed in each of the first to N-th wiring layers. Incidentally, the first wiring layer is the first layer from the main surface of the semiconductor substrate. The N-th wiring layer is the N-th layer from the semiconductor substrate.
The metal line 905 is exposed at the surface of the semiconductor integrated circuit device 900 to constitute an input/output pad 952. Metal lines (from a metal line 905 to a metal line 901) underlying the input/output pad 952 are electrically connected through plural plug contacts 921.
As shown in FIG. 10, the metal line 901 extends from a region of the input/output pad 952 to a region of the protective element 951. The metal line 901 further extends to overlap with a diffusion region 911. The metal line 901 is connected with the diffusion region 911 through plug contacts 922. A metal line 901′, which is separated from the metal line 901, is formed in the first wiring layer. The metal line 901′ is connected with the diffusion region 912 trough the plug contacts 922.
In the conventional semiconductor integrated circuit device 900, for example, any one of the first to N-th insulating layers is provided as a low dielectric-constant film in order to reduce a wiring capacity between the input/output pad and the protective element. Incidentally, the first insulating layer is the first layer from the main surface of the semiconductor substrate. The N-th insulating layer is the N-th layer from the main surface of the semiconductor substrate.
FIGS. 12A and 12B show another example of the conventional semiconductor integrated circuit device including an insulating layer having low dielectric constant. FIGS. 12A and 12B schematically show a power supply line of a conventional semiconductor integrated circuit device. FIG. 12A is a plan view of a conventional semiconductor integrated circuit device 800. FIG. 12B is a sectional view of FIG. 12A.
As shown in FIG. 12A, the semiconductor integrated circuit device 800 includes a Vcc line 801 and a GND line 802. The Vcc line 801 and the GND line 802 extend in parallel as viewed from above of the semiconductor integrated circuit device 800. As shown in FIG. 12B, the Vcc line 801 and the GND line 802 are formed adjacent to each other in the same wiring layer (k-th wiring layer).
However, in the conventional semiconductor integrated circuit device, various problems arise if a low dielectric-constant film is used (see, for example, S. Voldman et al., “High-Current Characterization of Dual-Damascene Copper Interconnects In SiO2— and Low-k Interlevel Dielectrics for Advanced CMOS Semiconductor Technologies”, IEEE International Reliability Physics Symposium, 1999, pp 144-153 or Japanese Unexamined Patent Publication No. 2005-129902 and No. 2005-223245).
The document of S. Voldman et al. describes that if an ESD (Electro Static Discharge) current flows through a line surrounded by an insulating layer that is a low dielectric-constant film, a breakdown strength (ESD tolerance) becomes lower than the case where an insulating layer is an SiO2 film.
Japanese Unexamined Patent Publication No. 2005-129902 discloses that a dielectric strength (TDDB: time dependent dielectric breakdown of oxide film) between upper and lower lines of a low dielectric-constant film is lower than a dielectric strength between upper and lower lines of a SiO2 film. Incidentally, Japanese Unexamined Patent Publication No. 2005-129902 also discloses a relation between a dielectric constant and a TDDB-resistance life. Japanese Unexamined Patent Publication No. 2005-223245 describes a problem that cracking occurs in a low dielectric-constant film below a bonding pad due to a stress or impact applied upon bonding, as a problem about a mechanical strength in the case of using a low dielectric-constant film for an insulating layer.
As described above, the conventional semiconductor integrated circuit device has a problem in that, if a low dielectric-constant film is used for an insulating layer to realize high-speed operations, breakdown strength, a dielectric strength, and a mechanical strength become lower.
The techniques of the document of S. Voldman et al. and Japanese Unexamined Patent Publication No. 2005-129902 and No. 2005-223245 cannot completely solve these problems. For example, the document of S. Voldman et al. describes only a design rule of the width of a Cu line as a low dielectric-constant film. Japanese Unexamined Patent Publication No. 2005-129902 discloses how to improve TDDB lifetime in terms of a manufacturing process and structure but does not disclose a relation between electric field strength of TDDB lifetime and a layout. Japanese Unexamined Patent Publication No. 2005-223245 discloses an ESD protective element formed below the pad but makes no reference to a relation between a current flowing through the line when the ESD protective element operates and a low dielectric-constant film.